This design was the analog front-end and digitization circuitry for a high speed infrared imaging system. The board included variable analog offset and gain circuitry that allowed for dynamic range improvement of the sampled video signal. Digitization was accomplished via 14 bit ADC converters which sampled the analog video signal at up to 20 MHz pixel rates. Communication with the image storage electronics was provided for via a LVDS ser/des chip set allowing extended cable runs with a very small signal count interface cable.
On-board voltage level converters allowed for clock and bias signal generation that could handle a wide variety of infrared focal plane array requirements.
Variable offset and gain op-amps in analog signal path.
14 bit ADC converters providing a 20 MHz pixel rate.
Programmable level controls on all clock and bias generation circuitry.
LVDS interface to storage electronics for extended cable lengths.